1. Field of the Invention
This invention generally relates to integrated semiconductor processes and to memory circuits and, more particularly, to single device memory circuits employing a diffusion storage capacitor for binary digits of information.
2. Description of the Prior Art
Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch, have achieved high memory cell densities. One of the simplest circuits for providing small memory cells is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. Each of these cells employs a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line. Conventional double polysilicon implementation of such cells required a shared contact for each cell. Consequently, the cell size tended to be large.
In also commonly assigned U.S. Pat. Nos. 4,080,590 by W. D. Pricer, and 4,040,017, by H. S. Lee, both filed Mar. 31, 1976, there are disclosed merged charge memories produced in a unipolar technology which is provided with very small cells, each of which includes substantially only a storage capacitor having a bit/sense line connected to one terminal of the capacitor and a word line which is selectively coupled to the other terminal of the capacitor. In the embodiments of these latter two patents, a direct current source of charges is produced at the surface of a semiconductor substrate and a plurality of inversion storage capacitors are formed also at the surface of the semiconductor substrate in a spaced apart relationship from the charge source. Voltage pulses representing binary digits are applied to one terminal of the capacitors and the other terminal of the capacitors is coupled to the direct current source of charges by the application of a word pulse to a word line. In order to preserve the information stored in the half-selected array cells while accommodating charge injection serially into the word-line accessed cells of both deep and shallow potential wells, only half of the charge capacity of the wells can be utilized as compared to the basic one device cell. Because the cells are accessed serially, its implementations forgo high speed read and write operations.
In an article entitled "A Capacitance-Coupled Bit-Line Cell for Mb Level DRAMS", by Masao Taguchi et al, in ISSCC Digest of Technical papers, Feb. 1984, pp. 100-101, a triple polysilicon capacitive-coupled bit line cell is used to achieve high storage capacitance. This structure requires a complex semiconductor process, and exhibits relatively poor topography and large cell area which are disadvantageous for high yield memory applications.